This invention relates to circuitry for handling serial data signals.
Circuitry that receives a serial data signal may need to perform various alignment tasks on that signal to render it more suitable for further processing. For example, a received serial data signal may include successive “bytes” of data (each including a predetermined number of successive bits) with no accompanying synchronization signal to tell the receiver circuitry where the byte boundaries are in the serial data. The receiver circuitry may deserialize the incoming data, and then test for proper bytes in the deserialized data. If proper bytes are not found when the serial data is deserialized in a particular way (i.e., assuming a particular “trial” byte boundary location), then different trial byte boundary locations are tried until proper bytes are found. The successful trial byte boundary location becomes the final byte boundary location, which is used for subsequent deserialization of the serial data.
Known byte alignment techniques include (1) clock stalling and (2) multiple multiplexer control. Both of these techniques may involve use of deserializer circuitry that shifts an incoming serial data signal into a shift register at the serial data bit rate, and periodically outputs the contents of the shift register in parallel at a byte rate (the byte rate being the bit rate divided by the number of bits in a byte). The clock stalling technique involves disabling the counter that converts the bit rate to the byte rate for one serial clock signal cycle. This causes the parallel output of the deserializer to shift (“slip”) one bit. The multiplexer control technique involves supplying the deserializer output signals to several different multiplexers and controlling the multiplexers to select different ones of their inputs until the selection causes the multiplexer outputs to collectively constitute a proper byte. Again, each successive trial multiplexer control selection typically causes the parallel output to shift or slip one bit.
Another example of a serial data signal alignment task that may need to be performed is “channel-to-channel” alignment to compensate for “skew” (loss of synchronization) between two or more serial data streams that are received via separate, parallel channels. Bit slipping may also be useful in performing such channel-to-channel alignment.
The known bit slipping techniques mentioned above may have certain disadvantages, such as relatively large size and limited numbers of bits that they can “slip” in an effort to do byte alignment and/or channel-to-channel alignment.